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A range of services can be provided covering the following main areas of the semiconductor design cycle:

  • Design for Test/Manufacture
    Test insertion
    Logic scan
    Memory BIST
    IEEE1149.1 and custom test startegies
    Design debug and analysis
  • Physical implementation
    Macro and full chip layout
    Physical verification
    Parasitic extraction and delay calulation
    Post layout verification of test programs
  • Test program development
    Automatic Test Pattern Generation
    Post-layout verification of test suites
    Pattern conversion to target ATE platform
    Test program debug
    Assistance with correlation and characterisation
  • Documentation
    Specification generation
    DFT, DFM specifications, DFT analysis design review
    Test coverage and quality expectations
    Final package test specification
    Wafer probe specifications
  • Training
    DFT, DFM training tailored to your needs and levels of company expertise
    Howto training in the specifics of DFT tooling usage and results - test insertion, build, Automatic Test Pattern Generation, event based simulation pattern generation

Dowd Associates

7 Barling Street, MacAndrew Bay, Dunedin 9014, New Zealand

Tel: +64 21024 19230

Email: Dowd Associates


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